VLSI low power (static and dynamic power dissipation) design is to minimize the individual components of power as much as possible, hence decreasing the total power consumption. Shift and short-circuit power make up the active power, whereas leakage current that passes through a hardware transistor makes up the static power. There are many techniques to design low power VLSI circuits such as CMOS power dissipation control, transistor level techniques, clock frequency, reduction of switching activity and scaling voltage. To compensate for the decrease in circuit performance introduced by reduced voltage, speed optimization is applied first, followed by supply voltage scaling, which brings the design back to its original timing, but with a lower power requirement. Low-power embedded design is driven by the need to run applications for as long as possible while consuming minimum power. All the electronic systems which are battery-powered systems need low power consumption, which implies lower cost of operation and smaller battery size to make applications more mobile, tabs, laptops and many more. The low-power verification focus is on ensuring that the design is electrically correct from a low-power perspective. The flow will verify that the isolation and retention are complete and correct as specified by the power intent.
The Ultra Low Power VLSI Design verification is next generation technology is considered in many areas can be achieved by Partial power-down, spurious phantom powering and latch-up, considering the impact of pull resistor, the low power design has disadvantages as well greater conductor size, large kVA rating of the equipment, large copper losses, poor voltage regulation. reduced handling capacity of the system and the cost of station and distribution equipment is more for a given load. For a low-power embedded system, extending battery-operated life or ensuring overall power efficiency are likely top priorities, you’ll need to develop requirements around your need for power efficiency. Low-power mode similarly disables many useful features, including background processes’ use of wireless communications. This limitation makes smartphones/tabs less, well, smart. Low power design is also required to reduce the power in high-end systems with huge integration density and thus improve the speed of operation. To optimize power dissipation specifically with low power methodology in digital systems, the method should be applied all over the design from system to process level.