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- Block/SoC level full ownership of RTL to GDSII
- Analog Block Integration
- Low Power Methodology
- Synthesis
- STA
- Floorplanning
- Placement and Routing
- Power Planning / Optimization
- Clock Tree Synthesis
- Cross-talk / Thermal / Noise Analysis
- IR drop and Signal Integrity Closure
- Physical Verification (DRC, LVS, ERC, Customer-specific Checks)
- ICC2, Innovus, Caliber, RC, DC, RedHawk, PT / PTSI
- TCL, SHELL, Perl & Python Scripting
- 5nm & Lower Nodes | UMC, TSMC, Intel, GF & more
- Logical Equivalence Check
We have a strong team of experts in DFT, Synthesis, PnR, STA and Physical Verification
We have successfully delivered projects on two Crypto Mining ASICs, SOCs for PCIE-Switch, Automotive and Consumer Electronics
We have expertise working with multiple fabs like TSMC, Samsung, Intel, GF, UMC, etc, and various technology nodes ranging up to 3nm
Physical Design
DFT – Design for Testability
- DFT Implementation – Scan Insertion, LBIST Insertion, Test Pin-Muxing
- Logic Insertion, Boundary Scan Insertion, Memory BIST Insertion and IOs
- ATPG, ATPG Verification
- Test pattern generation and Simulation
- Test mode timing constraints
- Coverage Improvement