Careers

Post 1 : Lead Engineer Design Verification

Job description : 

Work on design verification of state-of-the-art SOCs and/or IPs at cutting edge 6nm nodes for various customers. Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. 

Roles and Responsibilities : 

• Hands-on experience in UVM. C/C++ ,System Verilog verification language.
• Work on design verification of a complex IPs, Blocks, Sub-systems and SOC-level
• Guide and help junior engineers working on DV activities 
• Work hands-on on critical blocks/tasks
• Execute IP/SOC verification flows, and methodologies
• Responsible for implementing and analyzing system Verilog assertion and coverage(code, toggle, functional) .
• Work alongside other members of the verification team to analyze, develop and execute verification test cases and be able to provide relevant solutions to issues
• Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks
• Quality standards and good test and verification practices
• Expertise in PCI-e/USB/Ethernet/Switch protocol is an added advantage

Experience: 

• Design verification of IP-level, SoC -level and/or block-level/sub-system-level design
• Understanding of all phases of the IC design process from specification to post-Si

• Experience in high-speed, low-power, mixed-signal designs is a plus

• Experience in developing verification plan/verification methodology/flows from scratch

• Hands-on expertise with UMV (or similar) methodology, and Verilog/SystemVerilog(SV)

• Experience in low-power verification using UPF/CPF power intent flows is a plus

• Experience in constraint-random verification and/or transaction-based verification

• Experience in one or more of the IPs like LPDDR-4above, PCIE-Gen3 above, SATA, USB 3.0, Ethernet, DDR, NVMe

• Experience with on-chip protocols like AXI/AXI-Lite, AMBA/AHB/APB etc.

• Experience with gate-level simulations timing/no-timing

• Experience with one or more monitors, sequencers, drivers, scoreboards, checkers, coverage analysis/metrics, coverage closure, assertions, VIP components etc.

• Strong scripting skills with C/C++/Perl/Python

• Understanding of emulations platforms, S/W co-development, end-to-end verification

• EDA Tools: Industry standard tools from Synopsys, Cadence, Mentor etc.

Qualifications:

• BTech/MTech/PhD with 5-10 years experience in ASIC/SOC/IP design verification

• Proven track record with multiple successful ASIC/SOC design verification projects

• Proven ability to independently deliver results in a very fast-moving startup environment, be able to work hands-on as and when needed

• Be able to work under limited supervision and take complete accountability.

• Excellent written and verbal communication skills

Post 2 : Design Verification Engineer

Job Description :

• Create Verification Plans For Sub systems and IP Blocks
• Create Testbenches In SystemVerilog With UVM methodology
• Utilize Advanced Verification Techniques

Experience :

• Basic DPI programming 
• Skills In Object Oriented Programming (OOP), C, C++
• Experience With SystemVerilog
• Experience With The UVM Reuse Methodology
• Experience With Constrained Random Generation, 
• Coverage analysis – Functional and code Coverage
• Assertions and Formal connectivity checks
• Good Problem Solving And Debugging Skills

• Experience With One Or more simulators from the major EDA suppliers (Cadence, Mentor)
• Good Software Skills In Object Oriented Programming (OOP), C, C++, Perl, Tcl, Csh

Qualifications :

• BTech/MTech/PhD with 2-5 years experience in ASIC/SOC/IP design verification