How UVM Changed The Digital Design Verification World

UVM facilitates the construction of verification environments and tests, both by providing reusable machinery in the form of a library of SystemVerilog classes, and also by providing a set of guidelines for best practice when using System Verilog for verification.

Verification productivity can be enhanced by reusing verification components, and this is an important objective of UVM. Verification reuse is enabled by having a modular verification environment where each component has clearly defined responsibilities, by allowing flexibility in the way in which components are configured and used, by having a mechanism to allow imported components to be customized to the application at hand, and by having well-defined coding guidelines to ensure consistency.

The architecture of UVM has been designed to encourage modular and layered verification environments, where verification components at all layers can be reused in different environments. Low-level driver and monitor components can be reused across multiple designs-under-test. The whole verification environment can be reused by multiple tests and configured top-down by those tests. Finally, test scenarios can be reused from application to application. This degree of reuse is enabled by having UVM verification components able to be configured in a very flexible way without modification to their source code. This flexibility is built into the UVM class library.

The Universal Verification Methodology (UVM) is an open source SystemVerilog library allowing creation of reusable verification components and assembling test environments utilizing constrained random stimulus generation and functional coverage methodologies. UVM is a combined effort of designers and tool vendors, based on the successful OVM and VMM methodologies.

UVM Trends & Functional Verification Approaches

• The Universal Verification Methodology (UVM) is an open source SystemVerilog library allowing creation of reusable verification components and assembling test environments utilizing constrained random stimulus generation and functional coverage methodologies. UVM is a combined effort of designers and tool vendors, based on the successful OVM and VMM methodologies.